The use of configurable integrated circuits (“IC's”) has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (“FPGA”). An FPGA is a field programmable IC that has an internal array of logic circuits (also called logic blocks) that are connected together through numerous interconnect circuits (also called interconnects). In an FPGA, the internal array of logic and interconnect circuits is typically surrounded by input/output blocks. Like some other configurable IC's, the logic and interconnect circuits of an FPGA are configurable.
FIG. 1 illustrates a portion of a prior art configurable IC 100. As shown in this figure, the IC 100 includes an array of configurable logic circuits 105 and configurable interconnect circuits 110. The IC 100 has two types of interconnect circuits 110a and 110b. Interconnect circuits 110a connect interconnect circuits 110b and logic circuits 105, while interconnect circuits 110b connect interconnect circuits 110a to other interconnect circuits 110a. In some cases, the IC 100 includes hundreds or thousands of logic circuits 105 and interconnect circuits 110.
In some configurable IC architectures, an interconnect circuit 110b can connect to interconnect circuits 110b that are several columns or several rows away from it in the array. FIG. 2 illustrates several such connections in a prior configurable IC architecture 200. In the architecture 200, each logic circuit 105 forms a configurable computational tile 205 in conjunction with two neighboring interconnect circuits 110a and one neighboring interconnect circuit 110b. In each particular tile, each interconnect circuit 110a can receive inputs from the interconnect circuit 110b in the tile and supply a sub-set of the received input signals (e.g., one input signal) to the logic circuit 105 of the tile.
The interconnect circuits 110b in each particular tile serve as switchboxes that connect to other interconnect circuits 110b through intervening interconnect circuits 110a. As shown in FIG. 2, these switchboxes 110b can also connect to other switchboxes 110b that are two or more rows or columns away but in the same column or row. For instance, each switchbox can connect to switchboxes that are one, two, three and six rows above and below it, and to switchboxes that are one, two, three, and six columns to its right and left.
In the architecture of FIG. 2, a particular logic circuit 105 connects to logic circuits that are in the four tiles that are diagonally adjacent to the particular logic circuit's tile, through four connection boxes 110a in these tiles. For instance, FIG. 2 illustrates that the logic circuit 105 in tile 205a connects to the logic circuits 105 in tiles 205b-e through a connection box 110a in these tiles.
The advantage of the connection architecture illustrated in FIG. 2 is that it allows one computation tile to connect to another computational tile that is not a neighboring tile. On the other hand, this architecture requires the use of multiple connections to connect two tiles that are not diagonally adjacent and that are in two different rows and columns. This requirement makes the connection architecture illustrated in FIG. 2 inefficient and expensive as each connection requires the use of transistor switching logic.
Also, the connection architecture illustrated in FIG. 2 employs the same set of long connection schemes for each tile. Hence, as shown in FIG. 3, this architecture can result in a loop between two tiles 305 and 310 in the same column, or two tiles 315 and 320 in the same row. Such cycles are undesirable as they come at the expense of reachability of other tiles. The uniform connection architecture of FIG. 2 is also inefficient as it provides more ways than necessary for reaching one tile from another tile. This redundancy is illustrated in FIG. 3, which illustrates that the tile 325 can connect to tile 330 through two different sets of connections, one that goes through tile 335 and one that goes through tile 340. This redundancy is undesirable as it comes at the expense of reachability of other tiles.
Another example of a configurable IC is a VPGA. Like an FPGA, a VPGA includes configurable circuits. In a VPGA, at least some of the configurable circuits receive their configuration data from bit lines that supply configuration bits (e.g., 0 and 1 values) to various configurable circuits. In some embodiments, such a configurable circuit connects to such configuration bit lines through a set of vias that are defined to “configure” the configurable circuit. Such circuits are referred to below as via programmable (“VP”) configurable circuits.
Typically, the design and production of masks for ICs is very expensive. VPGAs are advantageous over other configurable ICs because some of the masks for the VPGA have already been defined. Therefore, only masks for certain layers (e.g., the customizable layers) of the VPGA need to be defined. As such, a VPGA has a much smaller non-recurring expenditures (“NRE”) than other configurable ICs.
Like some prior FPGA's, the architecture of current VPGA's use direct connections to connect vertically or horizontally aligned configurable circuits. Current VPGA's also use straight bit lines to provide the configuration bits to the configurable circuits. Such constraints on the architecture of current VPGA's have many of the same drawbacks as in the FPGA context.
There is a need in the art for a configurable IC that has a wiring architecture that increases the interconnectivity between its configurable circuits. Ideally, this wiring architecture is optimized for the interconnectivity between the configurable circuits of the configurable IC. Furthermore, such a wiring architecture can be used for a via programmable gate array (“VPGA”).